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INTEGRATED CIRCUITS
PCK2057 70 - 190 MHz I2C differential 1:10 clock driver
Product data Supersedes data of 2001 May 09 File under Integrated Circuits, ICL03 2001 Jun 12
Philips Semiconductors
Philips Semiconductors
Product data
70 - 190 MHz I2C differential 1:10 clock driver
PCK2057
FEATURES
* Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications supporting DDR 200/266/300/333
PIN CONFIGURATION
GND 1 Y0 2 Y0 3 VDDQ 4 Y1 5 Y1 6 GND 7 GND 8 Y2 9 Y2 10 VDDQ 11 SCL 12 CLK 13 CLK 14 VDDI2C 15 AVDD 16 AGND 17 GND 18 Y3 19 Y3 20 VDDQ 21 48 GND 47 Y5 46 Y5 45 VDDQ 44 Y6 43 Y6 42 GND 41 GND 40 Y7 39 Y7 38 VDDQ 37 SDA 36 FBIN 35 FBIN 34 VDDQ 33 FBOUT 32 FBOUT 31 GND 30 Y8 29 Y8 28 VDDQ 27 Y9 26 Y9 25 GND
* Full DDR solution provided when used with PCK2002P or
PCK2002PL, and PCK2022RA
* 1-to-10 differential clock distribution * Very low jitter (< 100 ps) * Operation from 2.2 V to 2.7 V AVDD and 2.3 V to 2.7 V VDD * SSTL_2 interface clock inputs and outputs * HCSL to SSTL_2 input conversion * Test mode enables buffers while disabling PLL * Tolerant of Spread Spectrum input clock * 3.3 V I2C support with 3.3 V VDDI2C * 2.5 V I2C support with 2.5 V VDDI2C * Form, fit, and function compatible with CDCV850
DESCRIPTION
The PCK2057 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs and one differential pair of feedback clock outputs. The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the 2-line serial interface (SDA, SCL), and the analog power input (AVDD). The two-line serial interface (I2C) can put the individual output clock pairs in a high-impedance state. When AVDD is tied to GND, the PLL is turned off and bypassed for test purposes. The device provides a standard mode (100 kbits) I2C interface for device control. The implementation is as a slave/receiver. The serial inputs (SDA, SCL) provide integrated pull-up resistors (typically 100 k). Two 8-bit, 2-line serial registers provide individual enable control for each output pair. All outputs default to enabled at power-up. Each output pair can be placed in a high-impedance mode, when a low-level control bit is written to the control register. The registers must be accessed in sequential order (i.e., random access of the registers is not supported). The I2C interface circuit can be supplied with either 2.5 V or 3.3 V (VDDI2C). Since the PCK2057 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power-up.
Y4 22 Y4 23 GND 24
SW00506
PIN DESCRIPTION
PINS 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 2, 3, 5, 6, 9, 10, 19, 20, 22, 23, 26, 27, 29, 30, 32, 33, 39, 40, 43, 44, 46, 47 4, 11, 21, 28, 34, 38, 45 13, 14, 35, 36 SYMBOL GND DESCRIPTION Ground Buffered output copies of input clock, CLK 2.5 V supply Differential clock inputs and feedback differential clock inputs Analog power Analog ground Serial data Serial clock I2C power
Yn, Yn, FBOUT, FBOUT VDDQ CLK, CLK, FBIN, FBIN
16 17 37 12 15
AVDD AGND SDA SCL VDD I2C
ORDERING INFORMATION
PACKAGES 48-Pin Plastic TSSOP TEMPERATURE RANGE 0 to +70 C ORDER CODE PCK2057DGG DRAWING NUMBER SOT362-1
2001 Jun 12
2
853-2253 26485
Philips Semiconductors
Product data
70 - 190 MHz I2C differential 1:10 clock driver
PCK2057
FUNCTION TABLE
INPUTS AVDD GND GND 2.5 V (nom.) 2.5 V (nom.) CLK L H L H CLK H L H L Y L H L H Y H L H L OUTPUTS1 FBOUT L H L H FBOUT H L H L Bypassed/OFF Bypassed/OFF ON ON PLL ON/OFF
NOTES: H = HIGH voltage level L = LOW voltage level 1. Each output pair (except FBOUT and FBOUT) can be put into a high-impedance state through the 2-line serial interface.
BLOCK DIAGRAM
SDA CONTROL LOGIC SCL Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 PLL FBIN FBIN AVDD Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 FBOUT FBOUT
CLK CLK
SW00507
2001 Jun 12
3
Philips Semiconductors
Product data
70 - 190 MHz I2C differential 1:10 clock driver
PCK2057
I2C ADDRESS
1
1
0
1
0
0
1
R/W
su01394
I2C CONSIDERATIONS
I2C has been chosen as the serial bus interface to control the PCK2057. I2C was chosen to support the JEDEC proposal JC-42.5 168 Pin Unbuffered SDRAM DIMM. All vendors are required to determine the legal issues associated with the manufacture of I2C devices. 1) Address assignment: The clock driver in this specification uses the single, 7-bit address shown below. All devices can use the address if only one master clock driver is used in a design. The address can be re-used for the CKBF device if no other conflicting I2C clock driver is used in the system. The following address was confirmed by Philips on 09/04/96. A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 0 NOTE: The R/W bit is used by the I2C controller as a data direction bit. A `zero' indicates a transmission (WRITE) to the clock device. A `one' indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller to WRITE data; the R/W bit of the address will always be seen as `zero'. Optimal address decoding of this bit is left to the vendor. 2) Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality required. Fast mode (400 kbits/s) functionality is optional. 3) Logic Levels: I2C logic levels are based on a percentage of VDD for the controller and other devices on the bus. Assume all devices are based on a 3.3 Volt supply. 4) Data Byte Format: Byte format is 8 Bits as described in the following appendices. 5) Data Protocol: To simplify the clock I2C interface, the clock driver serial protocol was specified to use only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. Indexed bytes are not allowed. However, the SMBus controller has a more specific format than the generic I2C protocol. The clock driver must meet this protocol which is more rigorous than previously stated I2C protocol. Treat the description from the viewpoint of controller. The controller "writes" to the clock driver.
1 bit Start bit
7 bits Slave Address
1 R/W
1 Ack
8 bits DUMMY
1 Ack DUMMY
1 bit Ack
8 bits Data Byte 1
1 Ack
8 bits Data Byte 2
1 Ack
1 Stop
SW00911
NOTE: The acknowledgement bit is returned by the slave/receiver (the clock driver). 6) Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in section 15 of the I2C specification. a) Pull-Up Resistors: Any internal resistors pull-ups on the SDATA and SCLOCK inputs must be stated in the individual datasheet. The use of internal pull-ups on these pins of below 100 k is discouraged. Assume that the board designer will use a single external pull-up resistor for each line and that these values are in the 5-6 k range. Assume one I2C device per DIMM (serial presence detect), one I2C controller, one clock driver plus one/two more I2C devices on the platform for capacitive loading purposes. (b) Input Glitch Filters: Only fast mode I2C devices require input glitch filters to suppress bus noise. The clock driver is specified as a standard mode device and is not required to support this feature. For specific I2C information, consult the Philips I2C Peripherals Data Handbook IC12 (1997).
2001 Jun 12
4
Philips Semiconductors
Product data
70 - 190 MHz I2C differential 1:10 clock driver
PCK2057
SERIAL CONFIGURATION MAP
The serial bits will be read by the clock buffer in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 All unused register bits (Reserved and "--") should be designed as "Don't Care". It is expected that the controller will force all of these bits to a "0" level. All register bits labeled "Initialize to 0" must be written to zero during initialization. Failure to do so may result in a higher than normal operating current.
Byte 0: Active/inactive register
1 = enable; 0 = disable BIT 7 6 5 4 3 2 1 0 PIN# 2, 3 5, 6 9, 10 19, 20 22, 23 47, 46 44, 43 40, 39 NAME CLK0, CLK0 CLK1, CLK1 CLK2, CLK2 CLK3, CLK3 CLK4, CLK4 CLK5, CLK5 CLK6, CLK6 CLK7, CLK7 INITIAL VALUE 1 1 1 1 1 1 1 1 DESCRIPTION Enable/Disable Outputs Enable/Disable Outputs Enable/Disable Outputs Enable/Disable Outputs Enable/Disable Outputs Enable/Disable Outputs Enable/Disable Outputs Enable/Disable Outputs
NOTE: 1. Inactive means outputs are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation.
Byte 1: Active/inactive register
1 = enable; 0 = disable BIT 7 6 5 4 3 2 1 0 PIN# 30, 29 27, 26 -- -- -- -- -- -- NAME CLK8, CLK8 CLK9, CLK9 -- -- -- -- -- -- INITIAL VALUE 1 1 0 0 0 0 0 0 DESCRIPTION Enable/Disable Outputs Enable/Disable Outputs Reserved Reserved Reserved Reserved Power-Down Mode Disable/Enable HCSL Enable/Disable
NOTE: 1. Inactive means outputs are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation.
2001 Jun 12
5
Philips Semiconductors
Product data
70 - 190 MHz I2C differential 1:10 clock driver
PCK2057
ABSOLUTE MAXIMUM RATINGS (see Note 1)
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). SYMBOL VDDQ/AVDD VDDI2C VI VO IIK IOK IO Tstg PARAMETER Supply voltage range I2C supply voltage range Input voltage range Output voltage range Input clamp current Output clamp current Continuous output current Continuous current to GND or VDDQ Storage temperature range except SCL and SDA SCL and SDA see Notes 2 and 3 see Notes 2 and 3 see Notes 2 and 3 VI < 0 or VI > VDDQ VO < 0 or VO > VDDQ VO = 0 to VDDQ TEST CONDITIONS LIMITS MIN 0.5 0.5 -0.5 -0.5 -0.5 -- -- -- -- -65 MAX 3.6 4.6 VDDQ + 0.5 VDDI2C + 0.5 VDDQ + 0.5 50 50 50 100 +150 UNIT V V V V V mA mA mA mA C
NOTES: 1. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 3.6 V maximum.
RECOMMENDED OPERATING CONDITIONS (see Note 1)
SYMBOL PARAMETER VDDQ Supply voltage AVDD VDDI2C CLK, CLK, HCSL buffer only VIL LOW-level input voltage g CLK, CLK FBIN, FBIN SDA, SCL CLK, CLK, HCSL buffer only VIH HIGH-level input voltage g CLK, CLK FBIN, FBIN SDA, SCL DC input signal voltage VID VIX IOH IO OL SR Differential input signal g voltage HIGH-level output current LOW-level LOW level output current Input slew rate SSC modulation frequency SSC clock input frequency deviation Tamb Operating free-air temperature SDA see Figure 3 DC: CLK, FBIN AC: CLK, FBIN see Note 3 see Note 4 see Note 4 see Note 5 see Note 2 TEST CONDITIONS LIMITS MIN 2.3 2.2 2.3 -- -0.3 -- -- 0.66 0.4 VDDQ/2 + 0.18 0.7 x VDDI2C -0.3 0.36 0.2 0.45 x (VIH - VIL) -- -- -- 1 30 0 0 TYP -- -- -- 0 -- -- -- 0.71 -- -- -- -- -- -- -- -- -- -- -- -- -- -- MAX 2.7 2.7 3.6 0.24 VDDQ - 0.4 VDDQ/2 - 0.18 0.3 x VDDI2C -- VDDQ + 0.3 -- -- VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 0.55 x (VIH - VIL) -12 12 3 4 33.3 -0.50 +70 UNIT V V V V V V V V V V V V V V V mA mA mA V/ns kHz % C
Input differential pair cross-voltage
NOTES: 1. Unused inputs must be held HIGH or LOW to prevent them from floating. 2. All devices on the I2C-bus, with input levels related to VDDI2C, must have one common supply line to which the pull-up resistor is connected. 3. DC input signal voltage specifies the allowable DC execution of differential input. 4. Differential input signal voltage specifies the differential voltage |VTR - VCP| required for switching, where VTR is the true input level, and VCP is the complementary input level. 5. Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the differential signals must be crossing. 2001 Jun 12 6
Philips Semiconductors
Product data
70 - 190 MHz I2C differential 1:10 clock driver
PCK2057
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. LIMITS SYMBOL VIK VO OH PARAMETER Input voltage HIGH level output voltage HIGH-level LOW-level LOW level output voltage SDA VOX II IOZ IDDPD IDD AIDD IDD I2C Output differential cross voltage Input current CLK, FBIN VDDQ = 2.7 V; VI = 0 V to 2.7 V VDDQ = 2.7 V; VO = VDDQ or GND CLK at 0 MHz; of IDD and AIDD CLK at 0 MHz; VDDQ = 3.6 V fO = 100 MHz fO = 100 MHz VDDI2C = 3.6 V; SCL and SDA = 3.6V VDDQ = 2.5 V; VI = VDDQ or GND High impedance state output current Power-down current on VDDQ + AVDD Power-down current on VDDI2C Dynamic current on VDDQ Supply current on AVDD Supply current on VDD Input capacitance I2C All inputs TEST CONDITIONS VDDQ = 2.3 V; II = -18 mA VDDQ = min to max; IOH = -1 mA VDDQ = 2.3 V; IOH = -12 mA VDDQ = min to max; IOL = 1 mA VDDQ = 2.3 V; IOL = 12 mA VDDI2C = 3.0 V; IOL = 3 mA MIN -- VDDQ - 0.1 1.7 -- -- -- VDDQ/2 - 0.2 -- -- -- -- -- -- -- 2 TYP1 -- -- -- -- -- -- VDDQ/2 -- -- 150 3 205 4 1 2.8 MAX -1.2 -- -- 0.1 0.6 0.4 VDDQ/2 + 0.2 10 10 250 20 230 6 2 3 UNIT V V V V V V V A A A A mA mA mA pF
VOL
CI
NOTES: 1. All typical values are at respective nominal VDDQ.
TIMING REQUIREMENTS
Over recommended ranges of supply voltage and operating free-air temperature. LIMITS SYMBOL fCLK Clock frequency Input clock duty cycle Stabilization time
1
PARAMETER
MIN 70 40 --
MAX 190 60 100
UNIT MHz % s
NOTE: 1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application.
TIMING REQUIREMENTS FOR THE I2C INTERFACE
Over recommended ranges of operating free-air temperature and VDDI2C from 3.3 V to 3.6 V.. STANDARD-MODE I2C-BUS SYMBOL fSCL tBUF tSU;STA tHD;STA tLOW tHIGH tr tf tSU;DAT tHD;DAT tSU;STO SCL clock frequency Bus free time between a STOP and START condition Set-up time for a repeated START condition Hold time (repeated) START condition. After this period, the first clock is generated. LOW period of the SCL clock HIGH period of the SCL clock Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals DATA set-up time DATA hold time Set-up time for STOP condition PARAMETER MIN -- 4.7 4.7 4.0 4.7 4.0 -- -- 250 0 4 MAX 100 -- -- -- -- -- 1000 300 -- -- -- UNIT kHz s s s s s ns ns ns ns s
2001 Jun 12
7
Philips Semiconductors
Product data
70 - 190 MHz I2C differential 1:10 clock driver
PCK2057
AC CHARACTERISTICS
LIMITS SYMBOL tPD tPHL ten tdis tjit(per) tjit(cc) tjit(hper) t tslr(o) tsk(o) PARAMETER Propagation delay time HIGH-to-LOW level propagation delay time Output enable time Output disable time Jitter (period); see Figure 4 Jitter (cycle-to-cycle); see Figure 5 Half-period jitter; see Figure 6 Static phase offset; see Figure 1 Output clock slew rate; see Figure 3 Output skew; see Figure 2 SSC modulation frequency SSC clock input frequency deviation NOTE: 1. This time is for a PLL frequency of 100 MHz. TEST CONDITIONS Test mode/CLK to any output SCL to SDA (acknowledge) Test mode/SDA to Y output Test mode/SDA to Y output 100 MHz to 167 MHz 100 MHz to 167 MHz 100 MHz to 167 MHz 133 MHz/VID on CLK = 0.71 V 167 MHz/VID on CLK = 0.71 V terminated with 120 /14 pF MIN -- -- -- -- -75 -75 -90 220 140 1 -- 30 0.00 TYP 3.7 500 85 35 -- -- -- -- -- -- -- -- --
1
MAX -- -- -- -- 75 75 90 450 270 2 75 33.3 -0.50
UNIT ns ns ns ns ps ps ps ps ps V/ns ps kHz %
AC WAVEFORMS
CLK CLK
FBIN FBIN t(O)n t(O)n + 1 n =N 1 N t(O)n (N is a large number of samples)
t(O) =
SW00882
Figure 1. Static phase offset
Yx Yx
Yx, FBOUT Yx, FBOUT tsk(O)
SW00883
Figure 2. Output skew
2001 Jun 12
8
Philips Semiconductors
Product data
70 - 190 MHz I2C differential 1:10 clock driver
PCK2057
80%
80% VID, VOD
20% CLOCK INPUTS AND OUTPUTS tSLR(I), tSLR(O) tSLR(I), tSLR(O)
20%
SW00886
Figure 3. Input and output slew rates
Yx, FBOUT Yx, FBOUT tcycle n
Yx, FBOUT Yx, FBOUT
1
fO tJIT(PER) = tcycle n - 1 fO
SW00884
Figure 4. Period jitter
tcycle n Yx, FBOUT Yx, FBOUT
tcycle n + 1
tJIT(CC) = tcycle n - t cycle n+1
SW00881
Figure 5. Cycle-to-cycle jitter
2001 Jun 12
9
Philips Semiconductors
Product data
70 - 190 MHz I2C differential 1:10 clock driver
PCK2057
Yx, FBOUT Yx, FBOUT thalf period n thalf period n + 1
1
fO tJIT(HPER) = thalf period n - 1 2*fO
SW00885
Figure 6. Half-period jitter
TEST CIRCUIT
VDD/2
PCK2057
C = 14 pf Z = 60 -VDD/2 R = 10 Z = 50
SCOPE
R = 50
Z = 60
R = 10
Z = 50
VTT
C = 14 pf -VDD/2
R = 50
VTT -VDD/2 NOTE: VTT = GND
SW00912
Figure 7. Output load test measurement
2001 Jun 12
10
Philips Semiconductors
Product data
70 - 190 MHz I2C differential 1:10 clock driver
PCK2057
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
2001 Jun 12
11
Philips Semiconductors
Product data
70 - 190 MHz I2C differential 1:10 clock driver
PCK2057
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Date of release: 06-01 Document order number: 9397 750 08476
Philips Semiconductors
2001 Jun 12 12

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